A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology

A 2R2W SRAM is presented targeting the increasing on-die bandwidth requirements of ML applications. The design features a 12T logic bit-cell optimized for low-voltage operation necessary for energy-aware ML accelerator designs, supporting a large operating voltage range and has power management features. The 6nm FinFET test chip is successfully validated to be fully functional down to 335mV. The design achieves a maximum of 135.6Tbps/W, providing an energy-efficient and high-bandwidth memory for ML applications.