A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation.

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)(2022)

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摘要
We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art.
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关键词
nonuniform period,retimed updating clock,nonlinearity calibration time,digitally controlled oscillator,DPLL-based phase modulator achieving -46dB EVM,fast two-step DCO nonlinearity calibration,nonuniform clock compensation,broadband digital PLL-based phase modulator,wide frequency modulation bandwidth,noise figure 46.0 dB
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