Stitching Process Development on 300mm Wafer CMOS BEOL for High Performance Chip Application

In this work, stitching process was developed on 300mm wafer CMOS BEOL for high performance chip application. Different stitching pattern and process was designed and implemented to verify the process performance, including different pattern overlap length, hammerhead dimensions, etc. Based on process data, optimized process condition was obtained to achieve better process performance.