High randomness hyperchaos-based parameterizable TRNG: Design, FPGA implementation and exhaustive security analysis

Recently, chaotic systems have become a thrilling discipline for information security applications, particularly in designing entropy sources. This paper presents a novel technique to tame an optimized 4D hyperchaotic Lorenz system by building a reconfigurable high randomness and low-cost hardware true random number generator (HC-HTRNG). Moreover, the proposed architecture has been modeled using the fourth-order Runge–Kutta method (RK4) and the 32 bits (10Q22) fixed-point arithmetic representation. The adopted methodology consists of two crucial points. First, we proposed using both intermediate and final solutions of the RK4 method as a raw data source for our HTRNG. The provided raw data are used to generate random numbers with parameterizable sizes. This approach reduces the design latency from four clock cycles to only one cycle while increasing the generation speed and the entropy value. Second, the designed HC-HTRNG integrates a FIPS 140-2-based built-in self-security test module (BISSTM). The BISSTM is used as an environment failure protection and testing mechanism (EFPTM) to guarantee online and continuous control of the proposed HC-HTRNG’s reliability and availability. Furthermore, the proposed HC-HTRNG has been implemented on the Xilinx ML605 FPGA platform using an RTL design based on the VHDL description of the RK4 method. A panoply of online/offline investigations and experiments were carried out intensely, deeply, and thoroughly to analyze, evaluate and validate the robustness and security aspects of the proposed HTRNG regarding all the aspects related to embedded system security. Notably, the evaluations were conducted regarding of chaos validation, security analysis, statistical tests, design performances, and comparisons. The investigations and implementation findings validate that the proposed architecture can attain high performance in terms of maximum post place and route operating frequency (MPRF) and throughput while occupying low FPGA space. Furthermore, timing and power efficiencies result presents an excellent trade-off between design efficiency and high-performance achievement. To the best of our knowledge, the proposed HC-HTRNG is the only one in the literature whose investigation has been subjected to 25 analyses, including 17 related to security aspects. Moreover, among all TRNGs, our generator is the only one that successfully passed seven statistical test suites, as well as the hardest and the most complex.