High Pressure Deuterium Annealing for Improved Immunity Against Stress-Induced Threshold Voltage Degradation

We demonstrate that high pressure deuterium (HPD) annealing presents effective process knob to achieve excellent threshold voltage ( $\text{V}_{\mathrm{ TH}}$ ) stability and superb electrical performance of MOSFETs. While devices without HPD annealing show significant negative shift in $\text{V}_{\mathrm{ TH}}$ , the device with HPD annealing exhibits excellent $\text{V}_{\mathrm{ TH}}$ stability under identical bias stress conditions. Due to the superior interface quality provided by HPD annealing, we achieve much lower SS and higher on-current along with negligible $\text{V}_{\mathrm{ TH}}$ shift, which is desirable for multi-threshold and high-performance logic device.