Editor’s notes: The authors present an IR-drop-based power-domain-s"/>
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Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements

Kazuki Monta,Leonidas Katselas,Ferenc Fodor,Takuji Miki,Alkis Hatzopoulos,Makoto Nagata,Erik Jan Marinissen

IEEE Design & Test（2022）

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Abstract
Editor’s notes: The authors present an IR-drop-based power-domain-scenario-based test methodology along with an in-field diagnosis technique. This utilizes on-chip monitor (OCM) circuits, and the toggle patterns can be designed with test pattern generation algorithms. —Vivek Chickermane, IBM Microelectronics
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Key words
Logic gates, System-on-chip, Clocks, Voltage, Very large scale integration, Integrated circuits, Testing
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