Design of Partial Product Generator Circuit for Approximate Radix-8 Booth Multiplier with Lower Delay

Booth’s algorithm is used to design fast multipliers. An approximate radix-8 booth multiplier reduces the number of steps for which the addition is done in the multiplication process. This algorithm encodes the multiplier bits and that is called Booth Recoding Process. Radix-8 booth recoding is done with grouping of 4 bits of multipliers. The main benefit of using radix-8 recoding is a faster circuit with an acceptable degradation in accuracy as it needs a bit large noise margin for logic 1 and logic 0. The multiplier consists of a left shift circuit to evaluate 2Q and 4Q and a circuit to determine 3Q (where Q is multiplicand). The partial product (PP) generator circuit is proposed to determine the partial product 3Q. In this proposed partial product (PP) circuit, a precise adder which have lesser propagation delay is used. Its delay is calculated and compared with other previously proposed circuits. The radix-8 approximate booth multiplier with proposed partial product generator having precise adder is faster than the accurate Booth multiplier. The logics circuit are designed and simulated on Cadence Virtuoso Analog Design Environment using 180 nm technology for NMOS and PMOS at supply voltage of 0.8, 1 and 1.8 V.