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Challenges for Sige Bicmos in Advanced-Node SOI

Jack Pekarik,Vibhor Jain, Crystal Kenney,Judson Holt,Shweta Khokale,Sudesh Saroop,Jeffrey Johnson,Kenneth Stein,Viorel Ontalus, Christopher Durcan,Mona Nafari,Tayel Nesheiwat,Sangameshwar Saudari,Elahe Yarmoghaddam,Saloni Chaurasia,Alvin Joseph

ECS Transactions（2022）

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Abstract
A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having f T/f MAX = 380/550GHz is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. The paper reviews advantages and challenges to integrating SiGe BiCMOS on an advanced node SOI technology.
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sige bicmos,advanced-node
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