An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology
IEEE Transactions on Circuits and Systems II: Express Briefs(2022)
摘要
In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. Measurement results based on 55nm CMOS process show that the proposed power-on-reset circuit consumes only 32nW at the supply voltage of 0.5V. The measured power-on-reset trip-voltage is 0.45V with a temperature coefficient of
$227~\mu \text{V}/^{\circ }\text{C}$
. Since the proposed power-on reset circuit consists of only 10 transistors, the area of the proposed power-on-reset circuit is as low as
$67.5~\mu \text{m}^{2}$
.
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关键词
Power-on-reset,low-voltage,low-power,high accuracy,area efficient
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