A 48-dB SFDR, 43-dB SNDR, 50-GS/s 9-b 2×-Interleaved Nyquist DAC in Intel 16

This work presents a 9-b 50-GS/s digital-to-analog converter (DAC) built in Intel 16 which combines $2\times $ -interleaving with improvements in the current steering cell and high-speed clock distribution to extend the state-of-the-art performance (SNDR, SFDR) to higher frequencies. The DAC consumes 243 mW from 0.8-V/1.0-V supplies at 50 GS/s with an active area of 0.2 mm2 and a worst-case 1/2-tone full-scale signal spur of −48.2 dBc, resulting in a linearity figure of merit (FoM) of 23.2 fJ/step. Measured SNDR of 43.2-dB results in an FoM of 41.3 fJ/step. These match the best reported FoMs above 10 GS/s while improving the speed and represent a $10\times $ or better improvement in each FoM compared to similar or faster speed DACs at $\sim 2\times $ lower swing than higher voltage designs. Feed-forward capacitors improve the step response of the current steering cell without additional area and only dynamic power consumption. AC-coupled coil-less clock buffers distribute the 25-GHz clock while attenuating duty cycle errors, eliminating the need for calibration within the sub-DAC. Duty cycle calibration is only needed at the final output switches with reduced correction range. These circuits together with efficient use of prior techniques now collectively applied extend the DAC’s speed with state-of-the-art performance at >20 GHz.