Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs

In order to keep up with scaling trends, significant efforts are being undertaken in the direction of vertical stacking of integrated circuits. With advancements in packaging technology, chips are being stacked atop each other using through-silicon-vias (TSVs). The fabrication process for TSVs on a silicon substrate for these 3D integrated circuits (ICs) introduces mechanical stresses that in turn affect the electrical parameters of the surrounding transistors depending on their orientation and distance from the TSV. This introduces significant variability in key performance metrics, especially when the devices operate at lower than nominal supply voltages. In this work, a complete methodology is developed to predict the impact on the delay of a buffer chain designed using Fin Field-Effect Transistors (FinFETs) around the TSV. First, an analytical model is developed to predict the normal stress components in the silicon wafer due to the TSV, which is subsequently converted in a layout-dependent model for variations in key device-level parameters. Subsequently, a modified logical effort-based model is proposed to predict the delay of a buffer chain designed around the TSV.