X-ray speed reading with the MCRC: a low noise CCD readout ASIC enabling readout speeds of 5 Mpixel/s/channel

The X-ray Astronomy and Observational Cosmology (XOC) group at Stanford University, in collaboration with the Massachusetts Institute of Technology (MIT) and MIT Lincoln Laboratory (MIT-LL), is developing next generation X-ray detector and readout technologies. Specifically, the XOC group is developing a fast, low noise readout application specific integrated circuit (ASIC) that is intended to be paired with X-ray charge-coupled device (CCD) detectors in development at MIT-LL. This readout ASIC is denoted as the MIT CCD Readout Chip or MCRC. The MCRC prototype is designed in a 350 nm technology node featuring 8 channels. Each channel is composed of two inputs. One is dedicated to read out the proven source follower-based (SF) CCD architecture with two selectable gain settings, an input referred noise of 1.63 e(RMS)(-), an input dynamic range of +/- 160 mV, channel to channel crosstalk less than -75 dBc, a power consumption of roughly 30 mW/channel, and a bandwidth of approximately 50 MHz, translating to an effective rise time of around 5 ns. Such a response can comfortably support readout speeds for large CCD pixel matrices in excess of 5 Mpixel/s/channel. The chip also features a second input which is an experimental drain-current readout (DR) topology to support Single electron Sensitive Read Out (SiSeRO) CCD stages currently in development at MIT-LL. The MCRC excels in speed while its input noise and bandwidth are on par with commercial discrete offerings, but with smaller power and real-estate footprints. Here we present the latest measurement results for this state-of-the-art prototype readout ASIC.