A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer

This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm(2). The input PGA can provide 0-18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC's SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s.