Successive approximation register ADC single event effects protection and evaluation

This work analyses seven different alternatives to implement an ADC based on the successive approximation register (SAR) architecture. The influence of the encoding is taken into account while evaluating the importance of its reset approach. Different protection strategies against single event upsets are addressed, including the comparison of per block and per cell triplication. All versions of the SAR were designed and prototyped in the TSMC 130 nm technology. The die was packaged in an open window QFN64 and irradiated at the LAFN Pelletron particle accelerator, which revealed the impact of the encoding and reset choices in the block cross-section showing improvements of more than a thousand times.