Electrical Characterization of highly stable 10nm triple-gate FinFET for different contacts and oxide region materials

Increasing dependencies on smart portable devices and requirement of longer battery back needs low power high speed, more reliable transistors for digital and memory applications. Vertical channel FinFET architecture is proved to be a suitable candidate for low-power digital logic and bulk memory design. This paper focuses on the design of 10nm triple-gate (TG) FinFET with the variation in different process parameters to examine for subthreshold parameters and transistor stability using device optimization techniques under different operating conditions. Presented FinFET (Fin-shaped FET) characterization is observed with the supply voltage of 1V and transconductance of 15mA/V. The optimization and effectiveness of the process parameters needed in FinFETs that is evaluated through the DC characteristics. The performance parameters like subthreshold slope, DIBL, transconductance (g m ), ON current (I on ), OFF current (I off ), threshold voltage (V th ), of FinFET are analyzed to attain highly stable TG FinFET. Simulation is performed for determining ON/OFF current ratio (I on /I off ), energy band diagram, hole/electron concentration, potential distribution and mobility of electrons according to the applied gate voltage. Also, the same parameters are analyzed by using different materials for source and drain contacts of TG FinFET. Higher current ratio (I on /I off ) and mobility enhancement are seen in the presented FinFET device having higher k-dielectric material at low voltage. The performance characteristics of the proposed TG FinFET with the variation in process parameters such as temperature, oxide thickness, doping level, channel length and W/L ratio are measured using TCAD device simulator.