Degradation of 650 V SiC double-trench MOSFETs under repetitive overcurrent switching stress

In this paper, the ruggedness of 650 V SiC double–trench MOSFETs (DT-MOS) under repetitive overcurrent switching stress was evaluated and investigated experimentally. The devices under test (DUTs) were electrically stressed by the hard switching transient as well as the conduction current nearly four times the rated one. It was shown that the threshold voltage (VTH) and on-resistance (RON) of DUTs increased after 100 K stress cycles, indicating the occurrence of performance deterioration. TCAD simulations revealed a similar failure mechanism with HTGB that the electrons injection into the gate oxide during the conduction stage should take the responsibility, which is totally different from the case of SiC planar-gate ones. What's more, the dependence of such degradation on the conduction duration TCD, overcurrent level IOL, driving condition VGS(ON/OFF) and gate resistors RG(ON/OFF) was researched comprehensively. The findings in this paper could provide indications to better drive such state-of-the-art SiC DT-MOS for long-term use in power electronic applications.