An Efficient Reconfigurable Encoder for the IEEE 1901 Standard
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2022)
Abstract
The IEEE 1901 standard for power line communication (PLC) enables simple connection among Internet of Things devices. The forward error correction (FEC) codes specified in the IEEE 1901 standard include low-density parity-check convolutional codes (LDPC-CCs) and Reed-Solomon convolutional concatenated (RSCC) codes. This work introduces an efficient reconfigurable encoder in full compliance with the IEEE 1901 standard. First, we propose a reconfigurable LDPC-CC encoder to fulfill the multirate requirement and improve the architecture by fine-tuned parallelization, which takes full advantage of the characteristics of the codeword structure. Then, for area reduction, the optimization regarding the RSCC encoder is extensively exploited. Moreover, the commonality between the encoders is discovered, and some circuitries are shared to reduce the hardware complexity. Equipped with these techniques, an efficient reconfigurable encoder for the IEEE 1901 standard is developed and implemented with 28-nm technology. Implementation results demonstrate that the proposed encoder can meet the throughput requirement of the IEEE 1901 standard and is both power- and area-efficient.
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Key words
Standards,Shift registers,Multiplexing,Delays,Forward error correction,Hardware,Convolutional codes,Fine-tuning,IEEE 1901 standard,parallelization,power line communication (PLC),reconfigurable hardware
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