A new extraction flow of the small-signal switch-HEMT model based on the parasitic resistance scanning algorithm

Recent research interest in switch High Electron Mobility Transistor (HEMT) modeling revealed the special modeling requirement that is a parasitic capacitance shell surrounding the equivalent circuit. Despite the robust determination of parasitic capacitances, one still may face several problems when extracting a small-signal switch-HEMT model. Practical switch-HEMT test structures include different configurations of gate network with additional microstrip lines, large-value resistors, and via-holes. Ignoring parts of these networks results in unfavorable errors when comparing measured and simulated results. Another problem may arise when extracting the switch-HEMT equivalent circuit parameters from the measured S-parameters of the grounded gate test structures: obtained parasitic resistances can be exaggerated, resulting in negative values of intrinsic channel resistance (conductance). This paper presents a new switch-HEMT extraction flow intended to address the mentioned challenges. To eliminate an excessive gate inductance attributed to via-hole, we introduce a concept of the gate network de-embedding. A negative channel resistance (conductance) problem is handled by applying a new parasitic resistance scanning algorithm that allows finding the model parameter vector with reasonable positive values in the vicinity of the S-parameters modeling error minimum. Accurate S-parameters modeling results verify the proposed extraction flow. Obtained small-signal switch-HEMT models are validated by designing and manufacturing a 2 dB digital step attenuator section.