System Design Technology Co-Optimization for 3D Integration at <5nm nodes

S.C. Song,Giri Nallapati,Irfan Khan, Nader Nikfar,Bohan Yan,Miguel Miranda,Bruce Lim,Mali Nagarajan,Joon-Young Park,Vaishnav Srinivas,Reza Langari,Bharani Chava, Venu Sanaka, Venu Boynapalli,Paras Gupta, Shree Pandey,Biancun Xie,Peijie Feng, Jihong Choi, Titash Rakshit, Ravi Shenoy,Mahadev Nemani,Colin Verrilli,John Zhu,Jun Chen,Mark Nakamoto,Lily Zhao,Yangyang Sun,Francois Atallah,Jonghae Kim,Rashid Attar,Chidi Chidambaram

2021 IEEE International Electron Devices Meeting (IEDM)（2021）

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摘要

Partition of monolithic 2D (M2D) chip and heterogeneous integration of resultant chiplets are inevitable in the near future due to rising cost of transistor and complexity of process. 3D stacking is required to maintain tight cross-IP communication and fit into the limited footprint over Printed Circuit Board (PCB). We discuss criteria of choice for the 3DIC technology flavor and logic chiplet scaling knobs in terms of optimized key performance indicators (KPI) at system level.

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System Design Technology Co-Optimization for 3D Integration at &lt;5nm nodes

System Design Technology Co-Optimization for 3D Integration at <5nm nodes