Opportunities in 3-D stacked CMOS transistors

M. Radosavljevic,C.-Y. Huang, W. Rachmady,S.H. Seung,N. K. Thomas, G. Dewey,A. Agrawal, K. Owens, C. C. Kuo, C. J. Jezewski, R. Nahm,N. Briggs, T. A. Tronic, T. Michaelos,N. A. Kabir, B. Holybee, K. Jun, P. Morrow, A. Phan,S. Shivaraman,H. W. Then, V. Kapinus, M. K. Harper, P. D. Nguyen, K. L. Cheong,S. Ghose,K. Ganguly,C. Bomberger, J. M. Tan, M. Abd El Qader,A. A. Oni, P. Fischer, R. Bristol,M. Metz, S. B. Clendenning, B. Turkot, R. Schenker, M. J. Kobrinsky, J. Kavalieros

2021 IEEE International Electron Devices Meeting (IEDM)（2021）

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摘要

3-D stacked CMOS transistors offer an opportunity to enable further standard cell and SRAM scaling, making them a promising transistor architecture to extend Moore's law. We review state-of-the-art approaches for achieving 3-D CMOS stacking. The sequential approach is highlighted by fabricating Ge PMOS stacked via layer transfer on top of Si NMOS, and self-aligned approach is demonstrated by simultaneously fabricated NMOS-on-PMOS multi-nanoribbon Si transistors. Both approaches showcase a well-balanced CMOS inverter built from transistors in top and bottom device layers.

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关键词

transistor architecture,sequential approach,CMOS inverter,3D CMOS stacking,3D stacked CMOS transistors,PMOS,SRAM scaling,Moore's law,NMOS-on-PMOS multinanoribbon silicon transistors,Ge,Si

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