First-principles Simulations of Tunneling FETs Based on van der Waals MoTe2/SnS2 Heterojunctions with Gate-to-drain Overlap Design

The electronic properties and transport properties of MoTe2/SnS2 heterostructure Tunneling FETs are investigated by the density functional theory coupled with non-equilibrium Green’s function method. Two dimensional (2D) monolayer MoTe2 and SnS2 are combined to a vertical van der Waals heterojunction. A small staggered band gap is formed in the overlap region, while larger gaps remain in the underlap source and drain regions of monolayer MoTe2 and SnS2 respectively. Such a type-II heterojunction is favorable for tunneling FET. Furthermore, we suggest short stack length and large gate-to-drain overlap to enhance the on-state current suppress the leakage current respectively. The numerical results show that at a low drain to source voltage Vds = 0.05V, On/Off current ratio can reach 108 and the On-state currents is over 20 μA/μm for n-type devices. Our results present that van der Waals heterostructure TFETs can be potential candidate as next generation ultra-steep subthreshold and low-power electronic applications.