Research on Low-Power Main Control Chip Architecture Based on Edge Computing Technology

Abstract With the continuous development of the times, chip technology has also been innovated. In order to meet the needs of edge computing networks and data communication networks, it is necessary to make chips with shorter delay time and lower power consumption, which in turn brings challenges to chip architecture design. In the field of chip design, the problem of chip performance has been overcome. In many edge design networks, the core of the design is to allow the chip to meet low power consumption requirements, thereby extending the use time of edge devices. This article conducts research on a low-power master chip architecture to enable it to meet the needs of edge computing networks and enhance product competitiveness.