A Novel Design of 16 Bit MAC Unit Based on Vedic Mathematics Using FPGA Hardware for Cognitive Radio Application

Vedic mathematics is the old approach of Indian mathematics, which takes an interesting method of figuring, depending continuously on 16 equations, which are received from “Vedas”. A multiplier is the essential part of numerical signal processors. The existing multipliers are designed with one stage, which lessens the carry usage of the Vedic mathematics also their use towards the mind-boggling multiplier guarantees generous decrease of propagation interruption happening examination through DA founded style then equal snake-based execution, which remains utmost generally utilized architectures. The usefulness of these paths remained patterned and the execution of boundaries similar to propagation delay and dynamic force utilization was determined by the Xilinx ISE Design Tool 14.7. This report proposes the arrangement of high-velocity Vedic propagation utilizing the procedures of Vedic propagation that is being altered to recover execution utilizing Carry-save adders. A high-velocity mainframe relies significantly upon the multiplier as it is one of the principal equipment blocks in most numerical signal handling agendas just as all-in-all processors. This chapter shows the architecture of a 16×16 multiplier module utilizing the Urdhva Tiryagbhyam sutra. The broadsheet at that point stretches out to 16×16 Vedic multiplier utilizing the “Nikhilam sutra” procedure. Furthermore, the Verilog HDL coding of the Urdhva Tiryagbhyam sutra and Nikhilam sutra for the duplication of 16x16 pieces and the carry-save snake is mimicked and executed on Xilinx ISE 14.7. A Vedic multiplier is a formula used in a cognitive radio network.