Failure Analysis Challenges of Phase Change Memory Test Structures with Two Case Studies

J. Demarest,N. Arnold,K. Brew,V. Chan, A. Cote,T. Gordon, M. Iwatake,G. Lian, J. Li,I. OK,S. McDermott,I. Saraf,N. Saulnier,L. Tierney, A. Varghese

International Symposium for Testing and Failure AnalysisISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis（2021）

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摘要

Abstract There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

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failure analysis,test,phase

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