Morphology and reliability aspects of 40 nm eSTM™ architecture

In this paper, we present an experimental study of a new architecture of the embedded Select in Trench Memory (eSTM™) cell. A first part is dedicated to a deep analysis of the overlap eSTM™ behaviour. A key fact is the possibility to achieve a large programming window thanks to tip effect enhanced erase. After the study on erase operation scheme, we demonstrate the impact of Select to Floating gate tip coupling on the endurance results. The endurance results are thus improved up to 500 k cycles using the overlap eSTM™.