Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique

Nowadays, high-end Field-Programmable Gate Arrays (FPGAs) are capable of implementing relatively high-performance systems in the field of Digital Signal Processing (DSP). Due to the abundant application of multipliers, their implementation efficiency and performance have become a critical issue in designing the DSP systems. On the other hand, FPGAs consume a large amount of power due to their complex circuitry. So, the power estimation of FPGA implementations at an early design stage has become a critical design metric. Various models are available in the literature based on Look-up Tables (LUTs), but not much literature is available on speed-optimized multiplier design using DSP slices only. In this paper, an embedded multiplier (12.0 IP core) has been analyzed and customized for different Input/Output (I/O) configurations to estimate the power using Vivado Design Suite (2014.4) targeted to the Zynq-family FPGA device (Zynq evolution and development kit). The embedded multiplier IP has been optimized for performance using two different approaches, i.e., Mults (DSP)-based and LUTs-based. Post-synthesis attributes have been used for formulating the power estimation models based on Artificial Neural Network (ANN) and curve fitting and regression technique. The power values estimated from the proposed models have been authenticated with reference to those assessed from the commercial tool. Based on the results obtained, ANN-based model provides average errors of 0.73% and 0.88% for the LUTs and DSP-based designs, respectively. Whereas, the model based on curve fitting and regression technique provides average errors of 3.61% and 1.59% for the LUTs and DSP-based designs, respectively. The timing analysis has been done to get the design performance and time complexity of the proposed models. Area analysis of the design has also been performed in order to report the resource utilization.