Design and Implementation of Synthetic Aperture Radar (SAR) Field-Programmable Gate Array (FPGA)-Based Processor

Featured Application Real-Time Processor for Synthetic Aperture Radar. Synthetic aperture radar (SAR) is a unique imaging radar system that is capable of obtaining high-resolution images by using signal-processing techniques while operating in all weather and in the absence of a light source. The potential of SAR in a wide range of applications has led to new challenges in digital SAR processor design. On-board storage of SAR raw data is often not practical for real-time applications. The design of digital SAR processors is always restricted by the available space of the carrier system, data transfer rate, payload capacity and on-board power supplies. As reported in the literature, although customized hardware solutions could offer the desired performance, they are not feasible for low-volume production. This research aims to design and develop an efficient digital SAR processor by using field-programmable gate array (FPGA) with the consideration of hardware resources, processing speed and precision. In this paper, a hardware implementation of an FPGA-based SAR processor is presented. The implementation and architecture of the proposed SAR processor are highlighted in this paper. A MATLAB-based SAR processing range-Doppler algorithm (RDA) was developed as the benchmark for the development of an SAR processor. The target device, Altera Stratix IV GX FPGA EP4SGX230KF40C2, was selected for the design and implementation of an FPGA-based SAR processor. Comprehensive evaluations of the performance of the proposed SAR processor in terms of precision, timing performance and hardware resource utilizations are also presented. The proposed FPGA-based digital SAR processor achieves optimum performance in processing SAR signals for image formation. Evaluation shows that the designed SAR processor is capable of processing SAR images with +/- 1% difference error as compared to SAR images processed by MATLAB. The results also show a reduction in hardware usage via the implementation of an FPGA-based FFT/IFFT coprocessor. These promising results prove that the performance of the proposed processor is satisfactory and the achieved processing time, as well as the power consumption of the processor, outperformed existing implementations.