Integration of Si0.7Ge0.3 fin onto a bulk-Si substrate and its P-type FinFET device fabrication

In this study, the integration of a high-mobility Si0.7Ge0.3 fin onto a bulk-Si substrate utilizing a shallow trench isolation (STI) last strategy and its fin field effect transistor (FinFET) device fabrication are investigated. A high-quality Si0.7Ge0.3 fin was first achieved by developing a process of the epitaxial growth of Si0.7Ge0.3, the fin etching of both the Si substrate and the Si0.7Ge0.3, the low-temperature STI densification annealing and the SiN liner. Then, a Si0.7Ge0.3 channel FinFET device was successfully fabricated by employing a newly developed spacer etching process, the annealing of a low temperature source and drain activation, an in-situ O-3 passivation process, and an Al2O3/HfO2 bi-layer gate dielectric. As a result, a drive current I (on) of 331 mu A mu m(-1) under V (DS) = V (GS) = -0.8 V was obtained without any strain-induced mobility enhancement technology. Using this bulk FinFET-compatible process, a high I (on)/I (off) ratio of similar to 5 x 10(5), an excellent subthreshold slope (SS) of 73 mV decade(-1) and a drain induced barrier lowering of 20 mV V-1 were demonstrated. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 fin is obtained after the fabrication of its FinFET device. The above results confirm that these newly developed processes can provide a potential solution for the integration of high-mobility channels onto a bulk Si substrate and its FinFET device fabrication.