A 16gb 27gb/s/pin T-coil Based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus
2022 IEEE International Solid- State Circuits Conference (ISSCC)（2022）
Key words
GDDR6 DRAM,merged-MUX TX,optimized WCK operation,alternative-data-bus,interface speeds,high-performance graphic applications,PAM4 signaling,reduced voltage margin,NRZ,circuit design,reduced power supply,speed enhancement,DRAM process,data bus,graphic DRAM,clock sampling margin,bit rate 27 Gbit/s,storage capacity 16 Gbit
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