A Hop-Parity-Involved Task Schedule for Lightweight Racetrack-Buffer in Energy-Efficient NoCs

Traditional NoC's buffer design mainly bases on SRAM that could not break through the high static power consumption characteristics by itself, which could be solved by emerging NVMs, such as energy-efficient RTM (Racetrack Memory). Using RTM instead of SRAM for NoC buffer design can directly reduce the static energy to near-zero level. However, RTM is not friendly to random access due to its port alignment operation, called invalid shift. This paper proposes to replace random FIFO-buffer with sequential LIFO-buffer for lightweight transmission in NoC, which can overcome the expense of invalid shift. However, the LIFO design incurs flits flipping during transmission and leads to extra endianess-correction cost in odd-path. Therefore, this paper designs a hop-parity-involved task schedule that avoids those odd-path during the communications among tasks, by which the extra endianess-correction can be totally removed. Our experiments show that RTM-LIFO buffer design can achieve over 50% energy saving than SRAM-FIFO buffer.