Scaling of Double-Gated WS2 FETs to Sub-5Nm Physical Gate Length Fabricated in a 300mm FAB
2021 IEEE International Electron Devices Meeting (IEDM)（2021）
关键词
high single-device yield,short-gate effects,unoptimized device configuration,short-gate control,connected dual gate configuration,improved device performance,physical gate length,gate length scaling,low channel mobility,moderate electric fields,low side contact resistance,double-gated FETs,FAB,field effect transistors,TCAD simulations,silicon FETs,thick CET,size 300.0 mm,size 2.0 nm,WS2
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