A novel FPGA-based convolution accelerator for addernet

In FPGA-based CNN accelerators, most of the multiplications in convolutions are realized by DSPs. Thus, the number of DSPs limits the parallelism of convolution computation. Recently proposed addernet replaces multiplications in convolution with additions. Based on addernet, we designed a novel PE in which the adders can be reused to perform replaced additions and accumulation. This PE can calculate a 3*3 convolution in 3 clocks using only 9 adders, and can be efficiently constructed on LUT with no DSP. On a Ultra-96 board which has 360 DSPs, we implement an accelerator with 60 proposed 3*3 PEs, and gain a throughput of 2.18 GOPs.