PASTE: FPGA-based Portable At-speed Scan Test Equipment

Abstract The increasing integration and complexity of chips driven by Moore’s Law has placed higher demands on chip verification and testing efforts. Automated Test Equipments (ATE) in conjunction with design for testability can effectively screen out faulty chips, but ATE is too costly and can be functionally redundant to be practical for small and medium-sized chip design companies and scientific research in universities. Therefore, in recent years, there has been a lot of research work on FPGA-based low-cost test equipment, but few studies have used the scan test method and have not been able to realize the at-speed test of the chip. In this paper, we propose a portable, low-cost and configurable FPGA-based chip scan test method, which can realize both normal and at-speed test, and can effectively filter the stuck-at faults and transition faults of the chip. We also optimize the test code size via run-length code compression algorithm and achieve a 68.16% compression rate for the test code, which effectively reduces the overall data storage and transmission overhead.