An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications

Chi Liu,Shao- Tzu Li,Tong-Lin Pan, Cheng-En Ni,Yun Sung,Chia-Lin Hu,Kang-Yu Chang,Tuo-Hung Hou,Tian-Sheuan Chang,Shyh-Jye Jou

2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)（2022）

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Abstract

A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and ...

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Key words

Resistance,Power demand,Voltage,Parallel processing,Very large scale integration,Real-time systems,Inference algorithms

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