Defect reduction in SiC epilayers by different substrate cleaning methods

Low defect epitaxial layers are of highest importance for the fabrication of high power SiC devices using large chip area. To minimize the impact of defects and particles on the substrates, the influence of different automated cleaning procedures on defects of epitaxial layers subsequently grown on 150 mm 4H–SiC substrates was investigated. Therefore, 12 μm thick n-type epitaxial layers were grown on commercially available 150 mm 4H–SiC Si-face substrates with lowest micropipe density using a warm-wall chemical vapor deposition reactor. The defects of all samples were characterized utilizing surface microscopy as well as ultra-violet photoluminescence techniques. With these methods, a qualitative, as well as quantitative, characterization of surface defects and crystallographic defects from the as-received substrate to the finished epitaxy was carried out and is discussed. Yield prediction maps for high voltage metal-oxide-semiconductor field-effect-transistors were generated and the reduction of critical defects, which results in a predicted die yield increase, as well as an outlook on future investigations, is discussed.