Improvement of sigma delta charge readout method for radiation detector application

Recently, a novel charge readout method has been developed based on 1-bit sigma delta modulation, which is able to directly achieve a Charge-to-Digital Conversion (QDC). This kind of design mainly comprises an amplifier and an FPGA instead of the conventional Front End Electronics (FEE) for radiation detectors. The amplifier is responsible for charge integration, and the FPGA is used for linear discharging. All of post-processing algorithms are implemented in the FPGA. Targeting this kind of readout method, some improvements are made to extend its application for new radiation detectors. In first improved version, a feedback resistor for baseline stabilization and a trigger threshold for removing noise signal are introduced. The feedback resistor leads to a slow exponential discharging when a charge signal is integrated on the feedback capacitor. To choose optimized parameters, an analysis of the exponential discharging effect on the linear discharging is made. In second version, an artful improvement is proposed to discard the exponential discharging. To evaluate the improved readout method, a 32-channel readout electronics prototype is developed. The performances and analysis of the circuit, such as channel linearity, dead time, are also presented. A SiPM based detector module is applied to verify this electronics prototype. The experimental results show that this new kind of charge readout is efficient and promising for other radiation detectors.