A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay

In this brief, a clock distribution scheme insensitive to supply voltage drift is proposed that minimizes variation of the clock propagation delay caused by the supply voltage change. While the overall clock distribution is composed of a current mode logic (CML) path and a CMOS path, most delay variations occur in the CMOS path. In the proposed scheme, delays in the CMOS path such as CML-to-CMOS c...