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A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC

Ashish Nayak,HsinChen Chen,Hugh Mair,Rolf Lagerquist,Tao Chen,Anand Rajagopalan,Gordon Gammie,Ramu Madhavaram,Madhur Jagota,CJ Chung,Jenny Wiedemeier,Bala Meera,Chao-Yang Yeh,Maverick Lin,Curtis Lin,Vincent Lin,Jiun Lin,YS Chen,Barry Chen,Cheng-Yuh Wu,Ryan ChangChien,Ray Tzeng,Kelvin Yang,Achuta Thippana,Ericbill Wang,SA Hwang

2022 IEEE International Solid- State Circuits Conference (ISSCC)（2022）

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摘要
This paper presents a tri-gear ARMv9 CPU subsystem incorporated in a 5G flagship mobile SoC. Implemented in a 5nm technology node, a 3.4GHz High-Performance (HP) core is introduced along with circuit and implementation techniques to achieve CPU PPA targets. A die photograph is shown in Fig. 2.5.7. The SoC integrates a 5G modem supporting NR sub-6GHz with downlink and uplink speed up to 7.01Gb/s an...
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关键词
Image resolution,Three-dimensional displays,5G mobile communication,Graphics processing units,Streaming media,Modems,Central Processing Unit
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