A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm

Bahram Zand,Mike Bichan,Alireza Mahmoodi,Mansour Shashaani,Jing Wang,Ruslana Shulyzki,James Guthrie,Katya Tyshchenko,Junhong Zhao,Eric Liu,Nima Soltani,Al Freeman,Rishi Anand,Syed Rubab,Ranjit Khela,Shaham Sharifian,Karl Herterich

2022 IEEE International Solid- State Circuits Conference (ISSCC)（2022）

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摘要

Demand for higher aggregate data rates in digital computing and storage services requires higher per-lane throughput, better reliability, and improved power- and area-efficiency. Support for a range of data transmission protocols in a single IP reduces risk, cost, and time to market. Beyond 56Gb/s, most SerDes IPs have adopted ADC-based architectures. While ADC-based receivers can offer higher lin...

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