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A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density

Wanik Cho,Jongseok Jung,Jongwoo Kim,Junghoon Ham,Sangkyu Lee,Yujong Noh,Dauni Kim,Wanseob Lee,Kayoung Cho,Kwanho Kim,Heejoo Lee,Sooyeol Chai,Eunwoo Jo,Hanna Cho,Jong-Seok Kim,Chankeun Kwon,Cheolioona Park,Hveonsu Nam,Haeun Won,Taeho Kim,Kyeonghwan Park,Sanghoon Oh,Jinhyun Ban, Junyoung Park,Jaehyeon Shin,Taisik Shin,Junseo Jang,Jiseong Mun,Jehyun Choi,Hyunseung Choi,Suna-Wook Choi,Wonsun Park,Dongkvu Yoon, Minsu Kim,Junvoun Lim,Chiwook An,Hyunyoung Shirr,Haesoon Oh,Haechan Park,Sungbo Shim,Hwang Huh,Honasok Choi,Seungpil Lee,Jaesuna Sim,Kichana Gwon,Jumsoo Kim,Woopyo Jeong,Jungdal Choi,Kyo-Won Jin

2022 IEEE International Solid- State Circuits Conference (ISSCC)（2022）

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Abstract
Triple-level-cell (TLC) NAND has prevailed the non-volatile memory market, yet the quad-level-cell (QLC) NAND is emerging as a suitable replacement for low-cost and high-density storage. However, despite its cost effectiveness QLC's market share is not increasing quickly, not only due to its worse reliability but also its slow sequential and random read performance. To increase random read perform...
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Key words
memory,improved read latency,4b/cell,d-nand
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