A 0.5–1 V, −68 Db Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-Nm CMOS
IEEE Journal of Solid-State Circuits（2022）
Key words
Voltage control,Time-domain analysis,Regulation,Bandwidth,Circuit stability,Gain,Stability analysis,Low-dropout (LDO) regulator,power supply rejection (PSR),voltage regulator,voltage-to-time converter (VTC)
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