Design of UAT Transceiver Based on ZIF Architecture

to address the need for low-cost and miniaturized test equipment for UAT data chain, a ZIF architecture 3U transceiver SDR platform based on FPGA and AD9361 is proposed. The RTL circuit is designed by Verilog HDL language to complete the IQ signal modulation and demodulation of 2CPFSK and RS coding circuit. RF output signal quality testing using test equipment and MATLAB proves that the method can achieve the data chain modulation and demodulation requirements. This method effectively reduces the cost and size of the UAT datalink transceiver and corresponding test equipment, and is an inspiration for ZIF generalized compact RF modems.