DESIGN METHODOLOGY FOR NARROW-BAND LOW NOISE AMPLIFIER USING CMOS 0.18 µm TECHNOLOGY

This paper presents a design methodology for a fully integrated narrow-band low noise amplifier (LNA). To demonstrate the effectiveness of the proposed methodology, an LNA for Wi-Fi and Bluetooth standards at 2.4 GHz is conducted. The design circuity is implemented using 0.18 µm TSMC CMOS technology, however; the methodology can be equally applied to any process node. Optimum transistor sizing and biasing to achieve minimum noise figure (NF) and maximum power gain without violating the specified power budget is attained by this methodology. It also specifies the criteria for choosing the on-chip RF inductors based on the quality factor, self-resonance frequency and area. The demonstrated LNA design achieves a power gain (S21) of 22.75 dB, input return loss (S11) of –30.11 dB, reverse isolation (S12) of –60.49 dB, and output return loss (S22) equals –11.23 dB. The linearity parameters of the P1-dB compression point and IIP3 are –19 dBm and –13.5 dBm, respectively. It produces a NF of 1.75 dB while consuming 6.16 mW from a 1.8 V power supply. [JJCIT 2022; 8(1.000): 98-111]