A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

Takashi Toi,Junji Wadatsumi,Hiroyuki Kobayashi,Yutaka Shimizu,Yuji Satoh,Makoto Morimoto,Rui Ito,Mitsuyuki Ashida,Yuta Tsubouchi,Mai Nozawa,Go Urakawa,Jun Deguchi,Ryuichi Fujimoto

IEEE Journal of Solid-State Circuits（2022）

引用 1|浏览15

暂无评分

摘要

This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers ...

查看译文

关键词

Bridge circuits,Topology,Downlink,Uplink,Transceivers,Jitter,Clocks

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要