Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

C. Maneux,C. Mukherjee,M. Deng, M. Dubourg,L. Reveil,G. Bordea,A. Lecestre,G. Larrieu,J. Trommer,E.T. Breyer,S. Slesazeck,T. Mikolajick,O. Baumgartner,M. Karner, D. Pirker,Z. Stanojevic,David Atienza,A. Levisse,G. Ansaloni, A. Poittevin, A. Bosio,D. Deleruyelle,C. Marchand, I. O'Connor

2021 IEEE International Electron Devices Meeting (IEDM)（2021）

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摘要

This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design-Technology Co-Optimization (DTCO) to achieve innovativ...

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关键词

Solid modeling,Three-dimensional displays,Computational modeling,Systems architecture,Computer architecture,Artificial neural networks,Transistors

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