Channel Surface Integrity with 2.4nm High-k Gate Dielectric under DPN Treatment at Different Annealing Temperatures

Using the analysis and comparison of electrical performance in gate leakage, drive current, transconductance, channel mobility, and interface-state density, the channel surface integrity with the higher annealing temperature under the fixed nitrogen concentration seems better than that with the lower one. The speculation is that the higher temperature provides the sufficiently thermal energy in repairs of traps in gate dielectric. Thus, the related high-k value is little increased, but the gate leakage due to the increase the Si-N bonds is somewhat raised, too. In general, using the higher annealing temperature at this fixed nitrogen concentration as a treatment still shows the better electrical performance for an nMOSFET except the channel surface integrity.