Power Loss Analysis of Three-Phase Four-leg Four-Wire Inverter Using SiC/Si HyS

Three-phase four-leg four-wire voltage source inverter (3P4L4W VSI) attracts more attention in many power electronics applications due to its flexibility for both balanced and unbalanced loads, where the power efficiency is a critical point. Conventional Si semiconductor devices suffer from large switching loss due to large parasitic capacitances and thus limit its switching frequency. As a result, it further limits the power density and efficiency improvement. The SiC/Si hybrid switch formed by SiC-MOSFET and Si-IGBT in parallel (SiC/Si HyS) can improve the switching frequency with high efficiency and low cost, which helps to design a power converter with high power density and high efficiency. However, the application of SiC/Si HyS in 3P4L4W faces some challenges, such as the drive circuit design, the proper delay selection, etc.. In this paper, a SiC/Si HyS based 3P4L4W VSI is introduced and the optimal turn-off time delay selection for the SiC/Si HyS used in 3P4L4W VSI is analyzed. A systematical way to calculate the power loss in the SiC/Si HyS is presented. A 5-kW/50kHz 3P4L4W VSI is taken as an example for validating the theory and method. It is found the peak efficiency of the 3P4L4W VSI is 97.5%, and the unbalanced phase load leads to more power loss and degrade the efficiency. The work in this paper provides practical guidance for a SiC/Si HyS based 3P4L4W VSI inverter design.