A Modified DPWM Method With Minimal Line Current Ripple and Zero-Sequence Circulating Current for Two Parallel Interleaved 2L-VSIs

High-performance comprehensive optimization of line current ripple, zero-sequence circulating current (ZSCC), and switching losses is a challenge for parallel interleaved inverters. This article proposes a modified discontinuous pulse width modulation (PWM) method for two parallel interleaved two-level voltage-source inverters (2L-VSIs), which are regarded as a single 3L-VSI to optimize its vector sequence. The line current ripple is the priority optimization target to guarantee the principle of the nearest three vectors is applied in each subsector. To reduce the ZSCC and switching losses, the vector combinations with smaller changing rate of ZSCC are selected, and the phase-leg carrying the highest current is clamped. The detailed design procedure of 3L-vector sequence and how to distribute to 2L-VSIs are revealed. The quantitative performance comparison between the proposed PWM method and existing ones in terms of line current ripple, ZSCC, and switching losses are made. Experimental results confirm the effectiveness of the proposed method.