Advanced multiple patterning technologies for high density hexagonal hole arrays

EUV lithography is moving forward to high volume manufacturing in DRAM production to overcome technological challenges in cell scaling. While EUV is confronting its own challenges, DRAM cell design rules have been scaled down using multiple patterning to extend the use of 193nm immersion lithography beyond its optical resolution limits . One of the big challenges in advanced DRAM nodes is to maintain the capacitance requirement while shrinking the capacitor size. By transitioning from square to honeycomb layout, the industry enabled taller capacitor s with larger diameters [1]. Those structures are patterned using spacer based pitch splitting techniques, but multi-patterning processes for capacitors need to ensure a high density arrays of holes are formed without losing critical dimension (CD) uniformity within the misalignment budget. In this work, we will demonstrate how to scale down capacitor pitch under 40nm using spacer based pitch splitting of lines and space to create honeycomb structures. Different strategies of self-aligned double patterning and quadruple patterning techniques to form a dense array of holes will be discussed. Furthermore, we will investigate how anti-spacer technique can play a role in local CD uniformity and placement in the final pattern.