Hardware Implementation of SHA Algorithms on Different FPGA and Speed Comparison

This paper presents a comparison of hardware efficiency of the current Secure Hash Algorithm (SHA) SHA-2 standard algorithm and Blake SHA-3 candidate realized on actual Intel field-programmable gate array (FPGA). The research methods are based on various platforms, which are based on pipelined methods, and folding and unrolling processes. Research is being conducted into bandwidth based on the speed and the overall usage of the resource of microcircuits. When creating hardware implementations of algorithms, overall performance is extremely necessary, and this parameter take into the system-wide comparative analysis.